Seminario FPGA-based Fault Injection – Jueves, 31/05-12:30h

Esta semana recibimos la visita del profesor José Luís Nunes, del Instituto Politécnico de Coimbra. Durante su visita, el profesor va a impartir este seminario en la sala de juntas del DISCA (2N-14), el jueves, 31 de mayo, a las 12:30h dirigido a estudiantes interesados de la rama de Ingeniería de Computadores y a los alumnos del Máster de Ingeniería Informática o de otros másters relacionados:

Title: FPGA-based Fault Injection

Summary: Reconfigurable embedded devices built on SRAM-based Field Programmable Gate Arrays (FPGA) are being increasingly used in critical embedded applications. Its susceptibility to Single Event Upsets (SEU) requires the use of fault tolerant designs, for which fault injection is one of the most accepted verification techniques.

In this talk implementation details of FIRED, a fault injector targeted at SRAM-based FPGAs (Virtex-5) for dependability evaluation of critical systems are presented. This tool is able to perform hardware fault injection in real-time, by inserting bitflips at the SRAM cells through Partial Dynamic Reconfiguration (PDR).

The architecture of an updated version of the tool, targetting current state-of-the-art devices (Xilinx 7-series) is also discussed. This new tool will take advantage of Soft Error Mitigation (SEM) core to support the fault injection.

CV of the speaker: José Luís Nunes is a professor at Coimbra Polytechnic where he teaches Operating Systems, Digital Systems and Computer Architectures. He is a member of the Software and Systems Engineering (SSE) research team at Center for Informatics and Systems of the University of Coimbra (CISUC), enrolled in the PhD program. His current research topics include dependability, fault injection, FPGAs and real-time embedded system.